This application is the national phase under 35 U.S.C. xc2xa7 371 of PCT International Application No. PCT/NO99/00365 which has an International filing date of Dec. 3, 1999, which designated the United States of America.
The present invention concerns a scalable data processing apparatus, particularly a data storage apparatus, comprising one or more thin-film devices which form a substantially planar layer generated by a number of sublayers of thin film, wherein the sublayers of thin film comprise electrical isolating and/or conducting and/or semiconducting structures and structures with information storage capability realized in a thin-film material in a sublayer, wherein the structures register with or contact electrically other structures of this kind in adjacent sublayers for realizing active and passive electronic circuits elements or logic cells in the thin-film device, wherein the active and passive circuit elements in a thin-film device are realized with a three-dimensional architecture and extend through two or more sublayers, wherein the circuit elements are electrically connected by horizontal electrical conducting structures in one or more sublayers and vertical electrical conducting structures extending through one or more of the sublayers, and wherein two or more thin-film devices are provided as an integrated stack of the substantially planar layers which form the thin-film devices, such that the apparatus forms a stacked configuration.
It is known in the art to create memory devices in the form of thin-film circuits in stacked configurations and wherein a memory device additionally may be combined with processors for controlling driving and addressing the memory, but then with the latter realized in inorganic semiconducting materials, either in the form of single crystal rigid substrates and/or thin-film provided on a carrier substrate which very well may be exceptionally thin, for instance formed as films of silicon dioxide. A complete memory device with processing circuits is created by juxtaposition of the layers and often with transfer of the thin-film circuits by means of special methods. In order to provide interconnections between the layers viz. through set of holes in the layers are used and possibly combined with evaporation of metal in order to create the necessary current paths. Further there is from PCT/NO99/00180 which belongs to the present applicant and which hereby is incorporated by reference, known an integrated scalable data processing device which forms a complete computer with a mass memory and a combined processor and memory module wherein either in separate processor layers or separate memory layers or combined processor and memory layers are provided so-called intelligent random access memories (IRAM) and processors which realize the CPU function of the computer or which realize control and communication functions in the computer. In order to provide short current paths three-dimensional electrical structures are used to create interconnections between components in the separate layers and between the layers mutually. The whole data processing device is provided on a substrate which contains further high-speed processing circuits for control and communication purposes, these being realized with inorganic semiconducting materials in conventional technology, while the different layers of the data processing device otherwise wholly are realized in thin-film technology whether they concern processors or memories.
Even though in the art known devices for data processing and storage based on the use of thin-film technology carry a number of advantages with regard to speed and functionality, they are for purely storage purposes often very costly and can particularly be complicated to produce. An effective memory management further requires a substantial processing capacity, for instance for control, communication and addressing, dedicated circuits for these purposes often being assigned a large memory or several separate memories with large storage capacity.
The main object of the present invention is to provide a scalable data processing apparatus, particularly a data storage apparatus which is relatively simple and inexpensive to make and which in principle allows for almost unlimited scaling of the data storage capacity without the management and operation of the memory becoming complicated.
A further object of the invention is to realize a scalable data processing apparatus, particularly a data storage apparatus substantially in thin-film technology which allows implementation of supporting functions for control and addressing of memories realized in thin-film technology, the electronic circuits for the mentioned purposes to be integrated with memories in the thin-film device.
Finally it is also an object of the present invention to realize a volumetric data storage device with large storage density, fast data access and high data transfer rate, optionally combined with parallel input of data in the data memory and fast parallel readout of data therefrom.
The above-mentioned and other objects are achieved according to the invention with a scalable data processing apparatus particularly a data storage apparatus, which is characterized in that each thin-film device comprises one ore more memory areas which form one or more matrix addressable memories, each with a memory medium in a sublayer in contact with a first electrode set in the form of stripe-like parallel electrical conducting structures or electrode structures and a second electrode set in the form of corresponding electrode structures oriented substantially orthogonal to the electrode structures in the first electrode set, the electrode sets respectively being provided in respective further sublayers adjacent to said sublayer on each side thereof, whereby addressable memory cells are created in the memory medium at the crossings between the electrode structures in the first and the second electrode set, that each thin-film device further comprises circuit areas which form electronic thin-film circuitry for controlling, driving and addressing the memory cells in one or more memories, said electronic circuitry being connected with electrode structures in respective the first and the second electrode set in a memory over current paths which are formed as electrical conducting structures in substantially the same sublayers wherein the electrode sets are provided, and that each thin-film device has a respective interface to every other thin-film device in the apparatus, said interfaces being realized with communication and signal lines and supporting circuitry for processing which extends vertically through respective dedicated interface areas in the thin-film device.
In an advantageous embodiment of the apparatus according to the invention the memory medium in one or more memories comprises materials selected among molecular materials in the form of monomers, oligomers or polymers, carbon-containing materials in inorganic or organic form, or a juxtaposition or mixture of such materials. In this connection it is preferred that the memory medium comprises a memory material which in a memory cell provides a non-linear current/voltage characteristic, said non-linear current/voltage characteristic being venerated by inorganic or organic diodes or a threshold-switchable material.
In another advantageous embodiment of the apparatus according to the invention the memory medium comprises a switchable material, said switchable material being a non-volatile material, selected as respectively a ferroelectric material or a charge transfer organic complex, or the memory medium can be switchable and have a non-linear current/voltage characteristic.
Advantageously can according to the invention the electronic circuitry comprise inorganic and/or organic semiconducting materials.
In an advantageous embodiment of the apparatus according to the invention the interface areas in one or more thin-film devices are provided integrated in an edge portion of this or these, said edge portions in the latter case registering mutually. In this connection it is preferred that the interface area in an edge portion additionally comprises an I/O interface for the respective thin-film device or optionally the apparatus as a whole, and implements functions for data and signal communication with external and/or peripheral devices.
Advantageously can in the apparatus according to the invention the thin-film device or the stacked configuration of such devices be that the thin-film device or the stacked configuration of such devices be provided on a substrate which comprises active electronic circuits for implementing additional control, driving and communication functions in the apparatus, each thin-film device being connected with a circuit over a separate interface area which in each case extends vertically through the thin-film devices which are located between a thin-film device in question and the substrate. In this connection it is preferred that the substrate comprises an interface portion that the substrate comprises an interface portion which extends substantially horizontally in the substrate and parallel to and adjacent to the thereabove provided thin-film device and which is electrically connected with the interface portions in thin-film device or the thin-film devices provided above the substrate, and particularly it is preferred that the interface portion that the interface portion further comprises an I/O interface for the apparatus as a whole, said I/O interface implementing functions for data- and signal communication with external and/or peripheral devices.
It is then also advantageous that the substrate is made in a semiconducting material, particularly an inorganic single crystal semiconducting material and even more particularly such a single crystal semiconducting material of silicon, and particularly it is in this connection preferred that the electronic circuits in the substrate are realized in CMOS technology. Further it is in this connection preferred that electrical connections between the electronic circuits in the substrate and its interface portion or over this interface portion to the interface areas in the above-lying thin-film devices are realized as CMOS-compatible metallic interconnections.
In an advantageous embodiment of the apparatus according to the invention wherein the apparatus comprises two or more thin-film devices, the thin-film devices are substantially conformal in the plane and provided mutually registering in the stacked configuration. In this connection it is preferred that one or more separation layers are provided interfoliated between adjacent thin-film devices and implementing either separately or in selected combinations respectively an electrical, thermal, optical or mechanical isolating function or a planarizing function, said interface areas in the respective thin-film devices in each case being electrically connected over vias in a respective separation layer.
In another advantageous embodiment of the apparatus according to the invention, wherein the apparatus comprises two or more thin-film devices, the thin-film devices are provided mutually staggered in the stacked configuration. In this connection it is preferred that one or more separation layers are provided interfoliated between adjacent thin-film devices and separately or in selected combinations implement respectively an electrical, thermal, optical or mechanical isolating or planarizing function, and that separation layers only are provided in the overlapping portion of two adjacent thin-film devices, the interface areas of the respective thin-film devices being provided above exposed surface portions of the thin-film devices in staggered area thereof, such that the separation layers between the thin-film devices form an unbroken layer without vias for electrical connections between the separate thin-film devices.
Finally can the apparatus according to the invention advantageously be provided on a carrier substrate formed of a foil-like material or a rigid material such as silicon, said carrier substrate in each case being provided adjacent to the lowermost thin-film device in the stacked configuration or an optionally provided substrate with electronic circuits.